Outphasing is a technique used to increase the efficiency of a power amplifier (PA) when it is not used at maximum output power (power back-off region). To achieve minimal power consumption the PA should achieve a high efficiency at peak power but also at power back off for modulating signals with varying envelope.
Conventional, non-switching PA's are typically quite inefficient at power back off, for example when amplifying AM modulated signals. Switching mode amplifiers on the other hand are usually non-linear, resulting in spectral spreading.
H. Chireix, “High power outphasing modulation,” Proceedings of the Institute of Radio Engineers, Vol. 23, No. 11, pp. 1370-1392, November 1935, hereinafter: Chireix, discloses an outphasing amplifier system. An example of an outphasing amplifier system is illustrated in FIG. 1. In an outphasing amplifier as shown in FIG. 1, the amplitude modulated (AM) signal is input to and split by a signal component separator 103 into two substantially constant envelope but phase modulated signals, so-called outphased signals. These two outphased modulated signals are then amplified by two identical amplifiers 101 and 102, respectively. The amplified signals produced by the amplifiers 101 and 102 are input to a power combiner 104. The power combiner 104 combines the two phase modulated signals into an amplified version of the original AM modulated signal that was the input of the signal component separator 103.
FIG. 2A illustrates certain principles of a power combiner 104. The voltage sources Vs1 and Vs2 represent the output of the power amplifier 101 and 102, respectively. The differential resistor RL represents a load.
The outphased sources may be represented, for example, byVs1=V(cos ϕ+j sin ϕ)Vs2=V(cos ϕ−j sin ϕ).wherein V denotes a voltage and j denotes the imaginary unit, and the outphasing angle is
  ϕ  =            arcsin      ⁡              [                              A            ⁡                          (              t              )                                            A            max                          ]              .  Herein, A(t) denotes the original amplitude modulated component of the input signal of the power combiner 104 and Amax denotes a maximum value of A(t).
The differential voltage across the load RL is VL=Vs1−Vs2=2 Vj sin ϕ. When ϕ is 90 degrees, maximum voltage swing may be obtained, for a ϕ of 0 degrees the differential voltage may be also 0 V.
The impedance each voltage source sees, is a function of the outphasing angle. The impedance Z1 seen by voltage source Vs1, and the impedance at Z2 as seen by the voltage source Vs2 have been indicated in FIG. 2A.
            Z      1        =                            V                      s            ⁢                                                  ⁢            1                                    (                                                    V                                  s                  ⁢                                                                          ⁢                  1                                            -                              V                                  s                  ⁢                                                                          ⁢                  2                                                                    R              L                                )                    =                                    R            L                    ⁢                                                    cos                ⁢                                                                  ⁢                Φ                            +                              j                ⁢                sin                ⁢                Φ                                                    2              ⁢                              j                ⁢                sin                ⁢                Φ                                                    =                                            R              L                        2                    ⁢                      (                          1              -                                                j                  ⁢                  cot                                〚                ϕ                )                                      〛                                ,          ⁢            Z      2        =                                        R            L                    2                ⁢                  (                      1            +                                          j                ⁢                cot                            〚              ϕ              )                                〛                    =                        Z          1          *                .            
Rewriting the impedance to a parallel equivalent provides:
      Y    1    =            1              Z        1              =                            2          ⁢                                    j              ⁢              sin                        (            ϕ            )                                                R            L                    ⁡                      (                                          cos                ⁢                                                                  ⁢                Φ                            +                              j                ⁢                sin                ⁢                Φ                                      )                              .      
FIG. 2B shows a diagram of Y1, the parallel equivalent of impedance Z1. FIG. 2C shows a diagram of Y2, the parallel equivalent of impedance Z2.
Multiplying with the complex conjugate and simplifying yields:
      Y    1    =                    2        ⁢                  sin          2                ⁢        ϕ                    R        L              +          j      ⁢                                    sin            ⁡                          (                              2                ⁢                ϕ                            )                                            R            L                          .            
The parallel equivalent circuit Y1 is shown in FIG. 2B with
      B    =                  R        L                    sin        ⁡                  (                      2            ⁢            ϕ                    )                      ,          ⁢      R    =                            R          L                          2          ⁢                      sin            2                    ⁢          ϕ                    .      
Similarly, the parallel equivalent circuit Y2, which is the complex conjugate of Z2, is shown in FIG. 2C.
When the output power is backed off and ϕ approaches 0, the reactive component value increases, which is undesirable for the efficiency. To compensate the efficiency loss for a certain outphasing angle, shunt reactances can be placed in parallel to cancel the reactive part of the load (Z1 and Z2), as disclosed by Chireix.
A non-isolating power combiner may be implemented with one or multiple transformers arranged in series, parallel or a combination of both. The simplest implementation is shown in FIGS. 2A, 2B and 2C, in which the load each PA sees is a function of the outphasing angle. To compensate the reactive part of each PA load at a certain outphasing angle, a compensation inductor Lcomp and a capacitor Ccomp can be added, as shown in FIG. 3A.
An isolating Wilkinson power combiner, shown in FIG. 3B, uses quarter wave (λ/4) transmission lines and forms a constant load for each PA, at the cost of a dissipating isolation resistor (Riso). If the isolation resistor is omitted, the combiner may behave as a non-isolating Chireix combiner.
Disadvantages of the implementations of power combiners described above, include that transformers use up large chip areas and are thus expensive elements. Transformers tend to be quite lossy or area consuming at industrial, scientific and medical (ISM) frequencies. Quarter wave transmission lines use up an even larger chip area and are only suited for chip integration at frequencies much above the ISM band. Load compensation Ccomp and Lcomp takes up additional elements, which take up further space on a chip.
Wenhua Chen, Karun Rawat, Fadhel M., “Multiband RF Circuits and Techniques for Wireless Transmitters”, discloses outphasing technique with a power combiner that sums the signals at the output of the power amplifiers to recover the amplitude modulation of the original signal. The isolated combiners such as Wilkinson or hybrid combiners are matched at all input and output ports independently from the magnitude and phase of their input signals. When input signals are out-of-phase, the mean efficiency degrades. The use of nonisolated power combiners, such as the Chireix combiner, avoids the power loss. However, the loads presented by the combiner at its input ports vary as a function of magnitudes and phases of the input signals. A cross-load modulation occurs between input ports. The PA's behavior, such as the gain, output power, and DC consumption, may vary. This type of combiners result in degradation of system linearity.